1. Field of the Invention
The present invention relates to a processor comprising cache memory having two or more layers of which the line sizes are mutually different, and, in particular, to a technique related to a processor equipped with a pre-fetch function applicable to the cache memory.
2. Description of the Related Art
A pre-fetch technique has conventionally been applied to a cache register in a computer executing a continuous access to memory used for a scientific calculation, such as a high performance computing (HPC), and the like.
The pre-fetch is a method for predicting instructions or data required in the near future and for reading them in cache memory or the like, and thereby a cache miss of the cache memory can be reduced.
Reference document 1 has disclosed a cache system equipped with a pre-fetch function. The system according to reference patent document 1 is configured to register, in a queue, a predicted address to be accessed next in the future distanced by a line size in a continuous access due to a cache miss when accessing memory data continuously and is configured to issue a pre-fetch instruction to the address to be accessed next in the future distanced by the line size by deciding that it is an event of continuous access, if the actual access address hits the queue, thus proving the prediction being correct.
If the line sizes between the upper layer cache memory and lower layer cache memory in multi-layered cache memory are different, the data size moved resulting from a cache miss in the lowest layer is any of the line size of the higher layer and of the lower layer. Further, in the case of a continuous access in which the function of a hardware fetch works, the case of the move-in data size being the lower layer line size of which the data size being the maximum exerts the highest performance and therefore the move-in data size is most possibly the data size of the lower layer cache memory in the above described case.
For example, in a memory system, the data size moved in by a cache miss is the line size of the lower cache in a memory access, while the data size is the line size of the higher cache in the case of a copy back.
In an HPC-series Job in which continuous access occurs in the majority of cases, a copy-back ratio is low, and therefore a move-in data size is highly possibly the line size of the lowest cache in the case of the above described continuous access.
Carrying out a pre-fetch in a cache memory system having different line sizes between the upper layer cache memory and lower layer cache memory causes the problem as follows.
If a data size moved in due to a cache miss in the lower layer is the line size of the lower layer cache, a request for a hardware pre-fetching issued from the upper layer cache to the lower layer cache (i.e., a request for a move-in to the lower layer cache) is only required for the line size of the lower layer cache. In the conventional cache system, however, the request is actually issued for each line size of the higher layer cache, resulting in the consuming of an extraneous lower layer cache access pipeline.
If a data size moved in due to a cache miss in the lower layer is the line size of the lower layer cache, a request for a hardware pre-fetching issued to the lower layer cache is only required for the line size of the lower layer cache. A hardware pre-fetching, however, sometimes loses a pre-fetch request due to implementation limitations, and in such a case of losing the request, only one issue of the pre-fetch request causes a failure in issuing a request for moving memory data into the lower layer cache.
If a data size moved in due to a cache miss in the lower layer cache register is the line size of the lower layer cache, a request for a hardware pre-fetching issued to the lower layer cache is only required for the line size of the lower layer cache memory. Therefore, if the address of a destination, which is next to upper layer cache memory by the line size thereof relative to the address which has been missed in the upper layer cache register is designated as the initial value of the pre-fetch address of a pre-fetch request, a lower layer cache access pipeline is wasted because of an extraneous pre-fetch request because there is a possibility that the address is the same line for the lower layer cache memory.
In the case of a continuous access to memory, in which a pre-fetch function works, a data size moved into the lower layer cache memory is highly possibly the line size of the lower layer cache and also possibly a data size different from the line size of the lower layer cache in some cases.
Patent document 1: Laid-Open Japanese Patent Application Publication No. 2004-38345